1. Field of the Invention
The present invention relates to a neutral beam-assisted atomic layer chemical vapor deposition (ALCVD) apparatus, and more particularly, to a neutral beam-assisted atomic layer chemical vapor deposition (ALCVD) apparatus and a method of processing a substrate using the same, capable of improving density of a planarization layer and preventing non-uniform deposition in the process of filling a gap or a shallow trench with an oxide layer by adding a neutral beam processing process.
2. Description of the Related Art
In general, chemical vapor deposition (CVD) is one of the industrial methods of forming a thin layer of, for instance, silicon on a substrate in the process of fabricating, for instance, an integrated circuit. In the CVD, when a gas including any chemical material is converted to plasma by heat, light or radio frequency energy, a raw material is converted to radicals, which are highly reactive, and is then adsorbed and deposited on a substrate.
Atomic layer deposition (ALD) refers to nanoscale thin layer deposition technology using a phenomenon of a mono-atomic layer that is chemically bonded during semiconductor fabrication, and enables layer-by-layer deposition, in which a deposited layer has the thickness of an atomic layer, by alternation between adsorption and substitution of molecules on the surface of a wafer.
Furthermore, the ALD may make deposited oxide and metal thin layers thin to the maximum extent, and may form a layer at a lower temperature than the CVD in which particles formed by a chemical reaction of the gas are deposited on a wafer surface, so that it is suitable for system-on-chip fabrication.
Further, in the case of a dynamic random access memory (DRAM), a trench pattern is formed using the CVD or ALD. This trench pattern is used for high density of a semiconductor device, and serves as a capacitor by forming a deep groove in a silicon substrate and generating capacitance between both sidewalls of the groove.
FIG. 1 is a roadmap for the pitch width and the trench aspect ratio in a DRAM. According to International Technology Roadmap for Semiconductor (ITRS) for the DRAM as illustrated in FIG. 1, 65 nm devices are mass-produced on a production line as of 2007.
In consideration of this trend, 45 nm devices may be mass-produced in 2009, and 32 nm devices may be mass-produced after 2012. It may be said that two processes, which are definitely applied to design rules for next-generation devices and thus make the devices fine, are a process of forming a gate pattern and a process of forming a trench pattern for electrical insulation
Here, the design rules specify that the upper width of a trench is sharply reduced, while the depth of a trench is not relatively reduced for stable insulation between the devices. Thus, the trench pattern shows a sharp increase in the aspect ratio (AR). The AR of the trench pattern may be supposed that at least 10 will be required after 2012.
When the trench pattern is formed, it is predicted that a silicon active pattern may be etched. However, this process has a difficulty in that, after the trench pattern is formed, a gap-fill process of filling the trench pattern with an oxide layer acts as a bottleneck.
FIG. 2 illustrates a trench depth and a gap-fill aspect ratio (AR) according to a technology node. As illustrated in FIG. 2, the upper width of a trench is considered for diversity within a wafer in the mass-production based on real process.
Since 45 nm class devices are based on a process for a large area of 300 mm, this diversity is expected to become stronger. The AR of the trench required for the trench gap-fill is about 10:1 or more. In the case of the CVD, high step coverage will be required.
Among the semiconductor processes, the deposition process associated with the gap-fill, such as a shallow trench isolation (STI) process, an interlevel dielectric (ILD) process, an inter metal dielectric (IMD) process, a pre metal dielectric (PMD) process, and a passivation process, has been performed using a high-density plasma chemical vapor deposition (HDPCVD) apparatus.
In contrast, in the case of 65 nm class devices, the gap-fill process using the HDPCVD apparatus encounters a limitation. As such, the deposition processes are carried out by other apparatuses using spin-on dielectric (SOD), sub-atmosphere chemical vapor deposition (SA-CVD), pulsed deposition layer (PDL) and so on. These apparatuses are also expensive, and thus have a difficulty in profile control, so that they have a problem in that a process capable of performing the gap-fill process in sub-65 nm class devices is required.